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I/O PLEXER Hardware Manual Appendices		A - Equivalent Communication Circuit B - I/O Performance C - Instruction Format (lengthy)

Appendix A - Equivalent Communication Circuit

Figure A-1 (below)  shows the equivalent RS-422/485 communication circuit for the I/O PLEXER. When switched to "Last Station" the 150 ohm network terminator resistors are in place.

Positions A-D of SW2 allow the removal/installation of network biasing resistors used to suppress line noise when all transmitters are at rest. These resistors should be left active on at least one, but not more than eight units in a single multidrop network segment. If more than eight resistor equipped units are present, transmitter overloading may occur.

Figure A-1  Electrical Equivalent Circuit

Appendix B - I/O Performance

The I/O PLEXER samples individual analog inputs at the constant rate of 100 samples per second. The effective sample rate per channel is determined by the total number of channels to be sampled.

Input data throughput is based on the time from the beginning of the first character of an instruction to the end of the last character of the response. The processing time of the host computer controlling input instructions will reduce the effective throughput.

Outout execution throughput is based on the time from the beginning of the first character of an instruction to the time when the actual output changes. Because the instruction acknowledgement response occurs before outputs actually change state, the processing time of the host computer controlling output instructions can reduce the effective throughput.

The tables below show msec per channel and channels per second for 1 and 16 I/O channel cases.

Digital Modules

Baud Rate	Output (Digital J)				Input (Digital M)
	1 Channel/IOP		16 Channels/IOP		1 Channel/IOP		16 Channels/IOP
	mSec/ Chan	Chan/ Sec	mSec/ 16 Chan	Chan/ Sec	mSec/ Chan	Chan/ Sec	mSec/ 16 Chan	Chan/ Sec
300	501	2	501	32	379	3	379	42
600	251	4	251	64	195	5	195	82
1200	126	8	126	127	104	10	104	154
2400	64	16	64	252	58	17	58	277
4800	32	31	32	496	35	29	35	458
9600	17	60	17	962	23	43	23	682
19200	9	113	9	1816	18	56	18	902
38400	5	203	5	3261	15	67	15	1076

Analog Modules

Baud Rate	Input (Analog L)				Output (Analog S)
	1 Channel/IOP		16 Channels/IOP		1 Channel		16 Channel
	mSec/ Chan	Chan/ Sec	mSec/ 16 Chan	Chan/ Sec	mSec/ Chan	Chan/ Sec	mSec/ 16 Chan	Chan/ Sec
300	639	2	2639	6	484	2	1984	8
600	323	3	1323	12	250	4	1000	16
1200	164	6	664	24	134	7	509	31
2400	85	12	335	48	75	13	263	61
4800	46	22	171	94	46	22	140	114
9600	26	39	88	181	32	32	78	204
19200	16	63	47	339	24	41	48	335
38400	11	91	27	602	21	48	32	494

The equations below can be used for determining mSec for any number of channels.

Throughput for digital I/O is independent of the number of channels.

DIRate = ((

(15Characters * 10Bits) BaudRate

) + 0.001mS ) * 1000mS

Figure B-1  Digital Input Data Time for 1-16 channels

DORate = ((

(11Characters * 10Bits) BaudRate

) + 0.012mS ) * 1000mS

Figure B-2  Digital Output Execution 1-16 channels

Throughput for analog I/O varies with the number of channels, n.

AIRate = ((

((15Characters  + ( 4 Characters*  NChannels)) * 10Bits) BaudRate

) + 0.006mS ) * 1000mS

Figure B-3  Analog Input Data Time for n channels.

AORate = ((

((11Characters  + ( 3 Characters*  NChannels)) * 10Bits) BaudRate

) + 0.017mS ) * 1000mS

Figure B-4 Analog Output Execution n channels.

The throughput for systems with a mixture of analog and digital data is determined by the sum of the time for each instruction using these equations.

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Appendix C - Instruction Format

Appendix C is the Protocol Instruction Set, which may be found here.

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